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12.4
Interrupts
During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The
interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.
12.5
Usage Notes
Contention between TCNT Write and Increment: If a timer counter clock pulse is generated
during the T
state of a write cycle to TCNT, the write takes priority and the timer count is not
3
incremented. See figure 12.8.
φ
TCNT
Internal write
signal
TCNT input
clock
TCNT
Figure 12.8 Contention between TCNT Write and Count up
Changing CKS2 to CKS0 Bit: Halt TCNT by clearing the TME bit to 0 in TCSR before
changing the values of bits CKS2 to CKS0.
CPU: TCNT write cycle
T
T
1
2
N
T
3
M
Counter write data
423
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