Block Diagram - Hitachi H8/3006 Hardware Manual

6.1.2

Block Diagram

Figure 6.1 shows a block diagram of the bus controller.
Internal address bus
WAIT
Internal signals
CPU bus request signal
DMAC bus request signal
DRAM interface bus request signal
CPU bus acknowledge signal
DMAC bus acknowledge signal
DRAM interface bus acknowledge signal
Legend
ABWCR : Bus width control register
ASTCR : Access state control register
WCRH
: Wait control register H
WCRL : Wait control register L
BRCR : Bus release control register
CSCR : Chip select control register
DRCRA : DRAM control register A
DRCRB
: DRAM control register B
RTMCSR : Refresh timer control/status register
RTCNT : Refresh timer counter
RTCOR : Refresh time constant register
BCR
: Bus control register
CS to CS
0 7
Area
decoder
Chip select
control signals
DRAM control
Figure 6.1 Block Diagram of Bus Controller
ABWCR
ASTCR
BCR
CSCR
Bus control
circuit
Wait state
controller
WCRH
WCRL
BRCR
Bus arbiter
BACK
BREQ
DRAM interface
DRCRA
DRCRB
RTMCSR
RTCNT
RTCOR
Internal signals
Bus mode control signal
Bus size control signal
Access state control signal
Wait request signal
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