φ
CS
to CS
5
2
(RAS
to
5
RAS
)
2
UCAS,
LCAS
RD (WE)
(High)
RFSH
20.3.5
TPC and I/O Port Timing
Figure 20.17 shows the TPC and I/O port input/output timing.
φ
Port 4,
6 to B
(read)
Port 4, 6,
8 to B
(write)
Figure 20.17 TPC and I/O Port Input/Output Timing
t
CSR2
t
CSR2
Figure 20.16 DRAM Bus Timing (Self-Refresh)
T
1
t
PRS
T
T
2
t
PRH
t
PWD
3
605