6.1.4
Register Configuration
Table 6.2 summarizes the bus controller's registers.
Table 6.2
Bus Controller Registers
1
Address*
Name
H'EE020
Bus width control register
H'EE021
Access state control register
H'EE022
Wait control register H
H'EE023
Wait control register L
H'EE013
Bus release control register
H'EE01F
Chip select control register
H'EE024
Bus control register
H'EE026
DRAM control register A
H'EE027
DRAM control register B
H'EE028
Refresh timer control/status register
H'EE029
Refresh timer counter
H'EE02A
Refresh time constant register
Notes: 1. Lower 20 bits of the address in advanced mode.
2. In modes 2 and 4, the initial value is H'00.
3. In modes 3 and 4, the initial value is H'EE.
4. For Bit 7, only 0 can be written to clear the flag.
Abbreviation
R/W
ABWCR
R/W
ASTCR
R/W
WCRH
R/W
WCRL
R/W
BRCR
R/W
CSCR
R/W
BCR
R/W
DRCRA
R/W
DRCRB
R/W
RTMCSR
R(W)*
RTCNT
R/W
RTCOR
R/W
Initial Value
2
H'FF*
H'FF
H'FF
H'FF
3
H'FE*
H'0F
H'C6
H'10
H'08
4
H'07
H'00
H'FF
109