Operation; Overview - Hitachi H8/3006 Hardware Manual

Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to
specify a fixed high level or fixed low level for the clock output, in addition to the usual switching
between enabling and disabling of the clock output.
Bit 7 Bit 1
GM CKE1
0 0
1
1
14.3

Operation

14.3.1

Overview

The main features of the smart card interface are as follows.
• One frame consists of 8-bit data plus a parity bit.
• In transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of
one bit) is provided between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for a1 etu period
10.5 etu after the start bit.
• If an error signal is detected during transmission, the same data is transmitted automatically
after the elapse of 2 etu or longer.
• Only asynchronous communication is supported; there is no synchronous communication
function.
Bit 0
CKE0 Description
0 Internal clock/SCK pin is I/O port
1 Internal clock/SCK pin is clock output
0 Internal clock/SCK pin is fixed at low output
1 Internal clock/SCK pin is clock output
0 Internal clock/SCK pin is fixed at high output
1 Internal clock/SCK pin is clock output
(Initial value)
497