Hitachi H8/3006 Hardware Manual page 356

Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T state of a general register read cycle, the value before input capture is read.
3
See figure 9.42.
φ
Address bus
Internal read signal
Input capture signal
GR
Internal data bus
Figure 9.42 Contention between General Register Read and Input Capture
340
General register read cycle
T T
1 2
GR address
X
X
T
3
M