Hitachi H8/3006 Hardware Manual page 307

When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter
and pins TCLKA and TCLKB become counter clock input pins. 16TCNT2 counts both rising and
falling edges of TCLKA and TCLKB, and counts up or down as follows.
Counting Direction
TCLKA pin
TCLKB pin
In phase counting mode channel 2 operates as above regardless of the external clock edges
selected by bits CKEG1 and CKEG0 and the clock source selected by bits TPSC2 to TPSC0.
Phase counting mode takes precedence over these settings.
The counter clearing condition selected by the CCLR1 and CCLR0 bits in 16TCR2 and the
compare match/input capture settings and interrupt functions of TIOR2, TISRA, TISRB, TISRC
remain effective in phase counting mode.
Bit 5—Flag Direction (FDIR): Designates the setting condition for the OVF flag in TISRC. The
FDIR designation is valid in all modes in channel 2.
Bit 5
FDIR Description
0 OVF is set to 1 in TISRC when 16TCNT2 overflows or underflows
1 OVF is set to 1 in TISRC when 16TCNT2 overflows
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode.
Bit 2
PWM2 Description
0 Channel 2 operates normally
1 Channel 2 operates in PWM mode
When bit PWM2 is set to 1 to select PWM mode, pin TIOCA
output goes to 1 at compare match with GRA2, and to 0 at compare match with GRB2.
Down-Counting
↑ ↓
High
↑
Low High
Up-Counting
↑
Low Low
↓ ↑
High
becomes a PWM output pin. The
2
↓
High
↓
Low
(Initial value)
(Initial value)
291