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14. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control
register) is set to 1.
15. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control
register) is cleared to 0.
16. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
set to 1, and bit CSEL in DRCRB (DRAM control register B) is cleared to 0.
17. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
set to 1, and bit CSEL in DRCRB (DRAM control register B) is set to 1; or, when bits
DRAS2, DRAS1, and DRAS0 are cleared to 0.
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