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8.7.2
Register Configuration
Table 8.11 summarizes the registers of port A.
Table 8.11 Port A Registers
Address*
Name
H'EE009
Port A data direction
register
H'FFFD9
Port A data register
Note:
*
Lower 20 bits of the address in advanced mode.
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
Bit
PA DDR
Initial value
Modes
3, 4,
Read/Write
Initial value
Modes
1, 2
Read/Write
A pin in port A becomes an output port if the corresponding PADDR bit is set to 1, and an input
port if this bit is cleared to 0. In modes 3 and 4, PA
address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 (modes 1 and 2) or H'80 (modes 3 and 4) by a reset and in hardware
standby mode. In software standby mode it retains it previous setting. Therefore, if a transition is
made to software standby mode while a PADDR bit is set to 1, the corresponding pin maintains its
output state.
Abbreviation
PADDR
PADR
7
6
5
PA DDR
PA DDR
7
6
5
1
0
0
—
W
W
0
0
0
W
W
W
R/W
W
R/W
4
3
PA DDR
PA DDR
4
3
0
0
W
W
0
0
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
DDR is fixed at 1 and PA
7
Initial Value
Modes 1, 2
Modes 3, 4
H'00
H'80
H'00
H'00
2
1
PA DDR
PA DDR
2
1
0
0
W
W
0
0
W
W
functions as an
7
0
PA DDR
0
0
W
0
W
263
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