Dram Interface Bus Timing - Hitachi H8/3006 Hardware Manual

20.3.4

DRAM Interface Bus Timing

DRAM interface bus timing is shown as follows:
• DRAM bus timing: read and write access
Figure 20.14 shows the timing of the read and write access.
• DRAM bus timing: CAS before RAS refresh
Figure 20.15 shows the timing of the CAS before RAS refresh.
• DRAM bus timing: self-refresh
Figure 20.16 shows the timing of the self-refresh.
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