Hitachi H8/3006 Hardware Manual page 566

External Clock: The external clock frequency should be equal to the system clock frequency
when not divided by the on-chip frequency divider. Table 18.3 shows the clock timing, figure 18.6
shows the external clock input timing, and figure 18.7 shows the external clock output settling
delay timing. When the appropriate external clock is input via the EXTAL pin, its waveform is
corrected by the on-chip oscillator and duty adjustment circuit.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (t
must remain reset with the reset signal low during t
Table 18.3 Clock Timing
Item Symbol Min
External clock input t
low pulse width
External clock input t
high pulse width
External clock rise t
time
External clock fall t
time
Clock low pulse t
width
Clock high pulse t
width
External clock t
output settling
delay time
Note: * t includes a 10 t
DEXT
V = 2.7 V
CC
to 5.5 V
Max
40 —
EXL
40 —
EXH
— 10
EXr
— 10
EXf
0.4 0.6
CL
80 —
0.4 0.6
CH
80 —
* 500 —
DEXT
of RES pulse width (t
cyc
) has passed after the clock input. The system
DEXT
, while the clock output is unstable.
DEXT
= 5.0 V ±
V = 3.0 V V
CC CC
to 5.5 V 10%
Min Max Min
30 — 15
30 — 15
— 8 —
— 8 —
0.4 0.6 0.4
80 — 80
0.4 0.6 0.4
80 — 80
500 — 500
).
RESW
Max Unit Test Conditions
— ns Figure 18.6
— ns
5 ns
5 ns
φ ≥ 5 MHz Figure
0.6 t
cyc
φ < 5 MHz
— ns
φ ≥ 5 MHz
0.6 t
cyc
φ < 5 MHz
— ns
µs
— Figure 18.7
20.3
553