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4.3
Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ
36 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT),
DRAM interface, 16-bit timer, 8-bit timer, DMA controller (DMAC), serial communication
interface (SCI), and A/D converter. Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
Interrupts
Notes: Numbers in parentheses are the number of interrupt sources.
1.
When the watchdog timer is used as an interval timer, it generates an interrupt
request at every counter overflow.
2.
When the DRAM interface is used as an interval timer, it generates an interrupt request
at compare match.
Figure 4-4 Interrupt Sources and Number of Interrupts
4.4
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a
start address from a vector table entry corresponding to a vector number from 0 to 3, which is
specified in the instruction code.
External interrupts
Internal interrupts
NMI (1)
IRQ to IRQ (6)
0
5
*1
WDT
(1)
DRAM interface
(1)
* 2
16-bit timer (9)
8-bit timer (8)
DMAC (4)
SCI (12)
A/D converter (1)
to IRQ
), and
0
5
73
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