Hitachi H8/3006 Hardware Manual page 178

Connection Examples
• Figure 6.29 shows typical interconnections when using two 2-CAS type 16-Mbit DRAMs
using a × 16-bit organization, and the corresponding address map. The DRAMs used in this
example are of the 10-bit row address × 10-bit column address type. Up to four DRAMs can
be connected by designating areas 2 to 5 as DRAM space.
H8/3006 and H8/3007
Figure 6.29 Interconnections and Address Map for 2-CAS 16-Mbit DRAMs with × 16-Bit
CS2 (RAS2)
CS3 (RAS3)
PB4 (UCAS)
PB5(LCAS)
RD (WE)
A10-A1
D15-D0
(a) Interconnections (example)
PB4
(UCAS)
15
H'400000
Area 2 DRAM (No. 1)
H'5FFFFE
H'600000
DRAM (No. 2)
Area 3
H'7FFFFE
H'800000
Area 4
H'9FFFFE
H'A00000
Area 5
H'BFFFFE
(b) Address map
Organization
2-CAS 16-Mbit DRAM
10-bit row address x 10-bit column address
x16-bit organization
RAS
UCAS
LCAS
WE
A9-A0
D15-D0
RAS
UCAS
LCAS
WE
A9-A0
D15-D0
PB5
(LCAS)
8 7 0
CS2 (RAS2)
CS3 (RAS3)
CS4
Normal
CS5
Normal
No.1
OE
No.2
OE
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