Table of Contents
Advertisement
19.6
Module Standby Function
19.6.1
Module Standby Timing
The module standby function can halt several of the on-chip supporting modules (SCI2, SCI1,
SCI0, the DMAC, 16-bit timer, 8-bit timer, DRAM interface, and A/D converter) independently in
the power-down state. This standby function is controlled by bits MSTPH2 to MSTPH0 in
MSTCRH and bits MSTPL7 to MSTPL0 in MSTCRL. When one of these bits is set to 1, the
corresponding on-chip supporting module is placed in standby and halts at the beginning of the
next bus cycle after the MSTCR write cycle.
19.6.2
Read/Write in Module Standby
When an on-chip supporting module is in module standby, read/write access to its registers is
disabled. Read access always results in H'FF data. Write access is ignored.
19.6.3
Usage Notes
When using the module standby function, note the following points.
DMAC: When setting a bit in MSTCR to 1 to place the DMAC or DRAM interface in module
standby, make sure that the DMAC or DRAM interface is not currently requesting the bus right. If
the corresponding bit in MSTCR is set to 1 when a bus request is present, operation of the bus
arbiter becomes ambiguous and a malfunction may occur.
DRAM Interface: When the module standby function is used on the DRAM interface, set the
MSTCR bit to 1 while DRAM space is deselected.
Cancellation of Interrupt Handling: Before setting a module standby bit, first disable interrupts
by that module. When an on-chip supporting module is placed in standby by the module standby
function, its registers are initialized, including registers with interrupt request flags.
Pin States: Pins used by an on-chip supporting module lose their module functions when the
module is placed in module standby. What happens after that depends on the particular pin. For
details, see section 8, I/O Ports. Pins that change from the input to the output state require special
care. For example, if SCI1 is placed in module standby, the receive data pin loses its receive data
function and becomes a port pin. If its port DDR bit is set to 1, the pin becomes a data output pin,
and its output may collide with external SCI transmit data. Data collision should be prevented by
clearing the port DDR bit to 0 or taking other appropriate action.
Register Resetting: When an on-chip supporting module is halted by the module standby
function, all its registers are initialized. To restart the module, after its MSTCR bit is cleared to 0,
its registers must be set up again. It is not possible to write to the registers while the MSTCR bit is
set to 1.
569
Advertisement
Table of Contents
