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8.8.2
Register Configuration
Table 8.15 summarizes the registers of port B.
Table 8.15 Port B Registers
Address*
Name
H'EE00A
Port B data direction register
H'FFFDA
Port B data register
Note:
*
Lower 20 bits of the address in advanced mode.
Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select
input or output for each pin in port B. When pins are used for TPC output, the corresponding
PBDDR bits must also be set.
Bit
PB DDR
7
Initial value
Read/Write
W
When a pin in port B becomes an output port if the corresponding PBDDR bit is set to 1, and an
input port if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. When transition is made to software standby mode while a PBDDR
bit is set to 1, the corresponding pin maintains its output state.
7
6
5
PB DDR
PB DDR
6
5
0
0
0
W
W
Abbreviation
PBDDR
PBDR
4
3
PB DDR
PB DDR
4
3
0
0
W
W
Port B data direction 7 to 0
These bits select input or output for port B pins
R/W
Initial Value
W
H'00
R/W
H'00
2
1
PB DDR
PB DDR
PB DDR
2
1
0
0
W
W
0
0
0
W
273
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