Hitachi H8/3006 Hardware Manual page 700

16TCR0—Timer Control Register 0
Bit
Initial value
Read/Write
Timer prescaler 2 to 0
Bit 2
TPSC2
0
1
Clock edge 1 and 0
Bit 4 Bit 3
CKEG1 CKEG0
0
0
1
Counter clear 1 and 0
Bit 6 Bit 5
CCLR1 CCLR0
0
0
1
0
1
1
7 6 5
CCLR1 CCLR0
1 0 0
R/W R/W
Bit 1 Bit 0
TPSC1 TPSC0
0
0
1
0
1
1
0
0
1
0
1
1
0 Counts on rising edge
1 Counts on falling edge
Counts on both rising and falling edges
16TCNT clearing disabled
16TCNT cleared by GRA compare match/input capture
16TCNT cleared by GRB compare match/input capture
Synchronous clear. 16TCNT cleared in synchronization with counter
clearing of other timers operating synchronously.
H'FFF68
4 3 2
CKEG1 CKEG0 TPSC2
0 0 0
R/W
R/W R/W
Description
Internal clock: Counts on φ
Internal clock: Counts on φ/2
Internal clock: Counts on φ/4
Internal clock: Counts on φ/8
External clock A: Counts on TCLKA pin input
External clock B: Counts on TCLKB pin input
External clock C: Counts on TCLKC pin input
External clock D: Counts on TCLKD pin input
Description
Description
16-Bit Timer Channel 0
1 0
TPSC1 TPSC0
0 0
R/W R/W
(Initial value)
(Initial value)
(Initial value)
687