Hitachi H8/3006 Hardware Manual page 374

Bit 6—Compare Match Flag A (CMFA): Status flag that indicates the occurrence of a TCORA
compare match or input capture.
Bit 6
CMFA Description
0 Clearing condition
Read CMFA when CMFA = 1, then write 0 in CMFA
1 Setting condition
8TCNT = TCORA
Bit 5—Timer Overflow Flag (OVF): Status flag that indicates that the 8TCNT has overflowed
(H'FF → H'00).
Bit 5
OVF Description
0 Clearing condition
Read OVF when OVF = 1, then write 0 in OVF
1 Setting condition
8TCNT overflows from H'FF to H'00
Bit 4—A/D Trigger Enable (ADTE) (8TCSR0): In combination with TRGE in the A/D control
register (ADCR), enables or disables A/D converter start requests by compare match A or an
external trigger. Bit 4 of 8TCSR2 is reserved, but can be read and written.
Bit 4
TRGE* ADTE
0 0
1
1 0
1
Note: * TRGE is bit 7 of the A/D control register (ADCR).
358
Description
A/D converter start requests by compare match A or an external trigger pin
(ADTRG) input are disabled
A/D converter start requests by compare match A or an external trigger pin
(ADTRG) input are disabled
A/D converter start requests by an external trigger pin (ADTRG) are enabled,
and A/D converter start requests by compare match A are disabled
A/D converter start requests by compare match A are enabled, and A/D
converter start requests by an external trigger pin (ADTRG) are disabled
(Initial value)
(Initial value)
(Initial value)