Hitachi H8/3006 Hardware Manual page 458

Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an
overrun error.
Bit 5
ORER Description
0 Receiving is in progress or has ended normally*
[Clearing conditions]
•
•
1 A receive overrun error occurred*
[Setting condition]
Reception of the next serial data ends when RDRF = 1
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its
previous value.
2. RDR continues to hold the receive data prior to the overrun error, so subsequent
receive data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 4—Framing Error (FER)/Error Signal Status (ERS): The function of this bit differs for the
normal serial communication interface and for the smart card interface. Its function is switched
with the SMIF bit in SCMR.
For serial communication interface (SMIF bit in SCMR cleared to 0): Indicates that data
reception ended abnormally due to a framing error in asynchronous mode.
Bit 4
FER Description
0 Receiving is in progress or has ended normally*
[Clearing conditions]
•
•
1 A receive framing error occurred
[Setting condition]
The stop bit at the end of the receive data is checked and found to be 0*
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous
value.
2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is
not checked. When a framing error occurs the SCI transfers the receive data into RDR
but does not set the RDRF flag. Serial receiving cannot continue while the FER flag is
set to 1. In synchronous mode, serial transmitting is also disabled.
The chip is reset or enters standby mode
Read ORER when ORER = 1, then write 0 in ORER
The chip is reset or enters standby mode
Read FER when FER = 1, then write 0 in FER
1
2
1
(Initial value)
(Initial value)
2
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