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Bits 2 to 0—Clock Select 2 to 0 (CSK2 to CSK0): These bits select whether the clock input to
8TCNT is an internal or external clock.
Three internal clocks can be selected, all divided from the system clock (φ): φ/8, φ/64, and φ/8192.
The rising edge of the selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
Some functions differ between channels 0 and 2 and channels 1 and 3.
Bit 2
Bit 1
CKS2
CKS1
0
0
1
1
0
1
Notes: 1. If the clock input of channel 0 is the 8TCNT1 overflow signal and that of channel 1 is the
8TCNT0 compare match signal, no incrementing clock is generated. Do not use this
setting.
2. If the clock input of channel 2 is the 8TCNT3 overflow signal and that of channel 3 is the
8TCNT2 compare match signal, no incrementing clock is generated. Do not use this
setting.
356
Bit 0
CKS0
Description
0
Clock input disabled
Internal clock, counted on rising edge of φ/8
1
Internal clock, counted on rising edge of φ/64
0
Internal clock, counted on rising edge of φ/8192
1
0
Channel 0: Count on 8TCNT1 overflow signal*
Channel 1: Count on 8TCNT0 compare match A*
Channel 2: Count on 8TCNT3 overflow signal*
Channel 3: Count on 8TCNT2 compare match A*
1
External clock, counted on falling edge
0
External clock, counted on rising edge
1
External clock, counted on both rising and falling edges
(Initial value)
1
1
2
2
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