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Figure 7.8 illustrates how normal mode operates.
Address T
A
Address B
A
Legend
L
= initial setting of MARA
A
L
= initial setting of MARB
B
N
= initial setting of ETCRA
T
= L
A
A
B
= L + SAIDE • (–1)
A
A
T
= L
B
B
B
= L + DAIDE • (–1)
B
B
Transfers can be requested (activated) by an external request or auto-request. An auto-requested
transfer is activated by the register settings alone. The designated number of transfers are executed
automatically. Either cycle-steal or burst mode can be selected. In cycle-steal mode, the DMAC
releases the bus temporarily after each transfer. In burst mode, the DMAC keeps the bus until the
transfers are completed, unless there is a bus request from a higher-priority bus master.
For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR).
SAID
DTSZ
• (2
• N – 1)
DAID
DTSZ
• (2
• N – 1)
Figure 7.8 Operation in Normal Mode
Transfer
Address T
B
Address B
B
215
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