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φ
t
AD
A
to A
,
23
0
CS
n
AS
RD
(read)
D
to D
15
0
(read)
HWR, LWR
(write)
D
to D
15
0
(write)
*
Note:
Specification from the earliest negation timing of A
T
1
t
cyc
t
t
CH
CL
t
Cf
t
ASD
t
AS1
t
ASD
t
AS1
t
ACC1
t
ASD
t
AS1
t
WDD
Figure 20.8 Basic Bus Cycle: Two-State Access
T
2
t
Cr
t
cyc
t
t
ACC3
SD
t
ACC3
t
RDS
t
SD
t
WSW1
t
WDS1
, CSn, and RD.
to A
23
0
t
PCH1
t
AH
t
t
RSD
PCH2
*
t
RDH
t
PCH1
t
AH
t
WDH
597
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