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10.5.2
A/D Converter Activation
The A/D converter can only be activated by channel 0 compare match A.
When the CMFA flag in 8TCSR0 is set to 1 and the ADTE bit is also set to 1, activation of the
A/D converter will be requested on generation of channel 0 compare match A. If the TRGE bit in
ADCR is set to 1 at this time, the A/D converter will be activated. When ADTE bit in 8TCSR0 is
set to 1, the A/D converter external trigger pin (ADTRG) input is disabled.
10.6
8-Bit Timer Application Example
Figure 10.17 shows how the 8-bit timer module can be used to output pulses with any desired duty
cycle. The settings for this example are as follows:
• Clear the CCLR1 bit to 0 and set the CCLR0 bit to 1 in 8TCR so that 8TCNT is cleared by a
TCORA compare match.
• Set bits OIS3, OIS2, OS1, and OS0 to (0110) in 8TCSR so that 1 is output on a TCORA
compare match and 0 is output on a TCORB compare match.
The above settings enable a waveform with the cycle determined by TCORA and the pulse width
detected by TCORB to be output without software intervention.
H'FF
TCORA
TCORB
H'00
TMO
372
8TCNT
Figure 10.17 Example of Pulse Output
Counter clear
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