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6.1.3
Pin Configuration
Table 6.1 summarizes the input/output pins of the bus controller.
Table 6.1
Bus Controller Pins
Name
Chip select 0 to 7
Address strobe
Read
High write
Low write
Wait
Bus request
Bus acknowledge
108
Abbreviation
I/O
CS
to CS
Output
0
7
AS
Output
RD
Output
HWR
Output
LWR
Output
WAIT
Input
BREQ
Input
BACK
Output
Function
Strobe signals selecting areas 0 to 7
Strobe signal indicating valid address output
on the address bus
Strobe signal indicating reading from the
external address space
Strobe signal indicating writing to the external
address space, with valid data on the upper
data bus (D
to D
)
15
8
Strobe signal indicating writing to the external
address space, with valid data on the lower
data bus (D
to D
)
7
0
Wait request signal for access to external
three-state access areas
Request signal for releasing the bus to an
external device
Acknowledge signal indicating release of the
bus to an external device
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