Clock - Hitachi H8/3006 Hardware Manual

14.3.5

Clock

Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register
(BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for
calculating the bit rate is shown below. Table 14.5 shows some sample bit rates.
If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is
output from the SCK pin.
B =
1488 × 2
where, N: BRR setting (0 ≤ N ≤ 255)
B: Bit rate (bit/s)
φ: Operating frequency (MHz)
n: See table 14.4
Table 14.4 n-Values of CKS1 and CKS0 Settings
n CKS1
0 0
1
2 1
3
Note: If the gear function is used to divide the clock frequency, use the divided frequency to
calculate the bit rate. The equation above applies directly to 1/1 frequency division.
Table 14.5 Bit Rates (bits/s) for Various BRR Settings (When n = 0)
N 7.1424
0 9600.0
1 4800.0
2 3200.0
Note: Bit rates are rounded off to one decimal place.
502
φ
× 10
6
× (N + 1)
2n–1
CKS0
0
1
0
1
10.00 10.7136
13440.9 14400.0
6720.4 7200.0
4480.3 4800.0
φ (MHz)
13.00 14.2848
17473.1 19200.0
8736.6 9600.0
5824.4 6400.0
16.00 18.00
21505.4 24193.5
10752.7 12096.8
7168.5 8064.5
20.00
26881.7
13440.9
8960.6