Hitachi H8/3006 Hardware Manual page 309

Bit 7
—
Initial value 1
Read/Write —
Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRA is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Input Capture/Compare Match Interrupt Enable A2 (IMIEA2): Enables or disables
the interrupt requested by the IMFA2 flag when IMFA2 is set to 1.
Bit 6
IMIEA2 Description
0 IMIA2 interrupt requested by IMFA2 flag is disabled
1 IMIA2 interrupt requested by IMFA2 flag is enabled
Bit 5—Input Capture/Compare Match Interrupt Enable A1 (IMIEA1): Enables or disables
the interrupt requested by the IMFA1 flag when IMFA1 is set to 1.
Bit 5
IMIEA1 Description
0 IMIA1 interrupt requested by IMFA1 flag is disabled
1 IMIA1 interrupt requested by IMFA1 flag is enabled
6 5
IMIEA2 IMIEA1 IMIEA0
0 0
R/W R/W R/W
Input capture/compare match interrupt enable A2 to A0
These bits enable or disable interrupts by the IMFA flags
4 3 2
— IMFA2
0 1 0
— R/(W)*
Input capture/compare match
flags A2 to A0
Status flags indicating GRA
compare match or input capture
Reserved bit
1 0
IMFA1 IMFA0
0 0
R/(W)* R/(W)*
(Initial value)
(Initial value)
293