Table of Contents
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List of Items Revised or Added for This Version
Page
Item
3
1.1 Overview
Table 1-1 Feature Watchdog timer (WDT)
28
2.6.1 Instruction Set Overview
35
Table 2-7 Bit Manipulation Instructions
41
2.6.5 Notes on Use of Bit Manipulation Instruction
Explanation
45
Table 2-13 Effective Address Calculation
57
Table 3-1 Operating Mode Selection
57
3.1.1 Operating Mode Selection
70
4.2.2 Reset Sequence
77
5.1.1 Features
144
Figure 6.15 Example of Wait State Insertion Timing
175
Figure 6.42 Example of Idle Cycle Operation (2)
(ICIS0 = 1)
(b) Idle cycle inserted
205
7.4.2 I/O Mode
Table 7.6 Register Functions in I/O Mode
207
7.4.3 Idle Mode
208
Table 7.7 Register Functions in Idle Mode
210
7.4.4 Repeat Mode
211
Table 7.8 Register Functions in Repeat Mode
226
7.4.8 DMAC Bus Cycle
248
8.3.2 Register Configuration
Port 6 Data Direction Register (P6DDR)
249
8.3.2 Register Configuration
Port 6 Data Register (P6DR)
253
8.5.1 Overview
Figure 8.4 Port 8 Pin Configuration
254
8.5.2 Register Configuration
Port 8 Data Direction Register (P8DDR)
Description
Specification description
amended
Number of instruction
types amended
Function description
added
Description added
No. 1 in Addressing Mode
and Instruction Format
column amended
Table amended
Description added
Description added
Description added
Figure amended
Bus cycle B amended
Description added
Description added
Description added
Description added
Description added
Description added
Note added
Description amended
Description amended
Reference changed
Description added
Description amended
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