Hitachi H8/3006 Hardware Manual page 114

IRQ
Yes
Figure 5-4 Process Up to Interrupt Acceptance when UE = 1
• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
• When the interrupt controller receives one or more interrupt requests, it selects the highest-
Program execution state
Yes
Priority level 1?
Yes
No
0
No
IRQ
1
Yes
TEI2
Yes
Interrupt requested?
Yes
NMI
No
No
IRQ
0
Yes
I = 0
Yes
Save PC and CCR
←
I 1
Read vector address
Branch to interrupt
service routine
No
Pending
No
No
IRQ
1
Yes
TEI2
Yes
No
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