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9.6
Usage Notes
This section describes contention and other matters requiring special attention during 16-bit timer
operations.
Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T
a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See
figure 9.37.
φ
Address bus
Internal write signal
Counter clear signal
16TCNT
Figure 9.37 Contention between 16TCNT Write and Clear
TCNT write cycle
T
T
1
2
16TCNT address
N
T
3
H'0000
state of
3
335
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