Hitachi H8/3006 Hardware Manual page 360

16-bit timer Operating Modes
Table 9.7 (a)16-bit timer Operating Modes (Channel 0)
Operating Mode
Synchronous preset
PWM mode
Output compare A
Output compare B
Input capture A
Input capture B
Counter By compare
clearing match/input
capture A
By compare
match/input
capture B
Syn-
chronous
clear
Legend: Setting available (valid). — Setting does not affect this mode.
Note: * The input capture function cannot be used in PWM mode. If compare match A and compare match B occur
simultaneously, the compare match signal is inhibited.
344
TSNC TMDR
Synchro-
nization MDF FDIR PWM
SYNC0 = 1 — —
— —
— —
— —
— —
— —
— —
— —
SYNC0 = 1 — —
Register Settings
TIOR0
IOA IOB
PWM0 = 1 —
PWM0 = 0 IOA2 = 0
Other bits
unrestricted
IOB2 = 0
Other bits
unrestricted
PWM0 = 0 IOA2 = 1
Other bits
unrestricted
PWM0 = 0 IOB2 = 1
Other bits
unrestricted
TCR0
Clear Clock
Select Select
*
CCLR1 = 0
CCLR0 = 1
CCLR1 = 1
CCLR0 = 0
CCLR1 = 1
CCLR0 = 1