Related Registers; Table 2.1.1 Pull-Up Control Register Pu0 - Renesas 4513 User Manual

APPLICATION
2.1 I/O pins
(7) Port D
D –D are eight independent I/O ports.
0 7
Input/output of port D
Each pin of port D has an independent 1-bit wide I/O function. For I/O of ports D
of port D with the register Y of the data pointer first.
Data input to port D
Set the output latch of specified port Di (i = 0 to 7) to "1" with the SD instruction.
When the output latch is set to "0," "L" level is input.
When the SZD instruction is executed, if the port specified by register Y is "0," the next
instruction is skipped. If it is "1," the next instruction is executed.
Data output from port D
Set the output level to the output latch with the SD and RD instructions.
The state of pin enters the high-impedance state when the SD instruction is executed.
The states of all port D enter the high-impedance state when the CLD instruction is executed.
The state of pin becomes "L" level when the RD instruction is executed.
The output structure is an N-channel open-drain.
Notes 1: When the SD and RD instructions are used, do not set "1000
2: Port D
using ports D
W6 to "0."

2.1.2 Related registers

(1) Pull-up control register PU0
Register PU0 controls the ON/OFF of the ports P0
Set the contents of this register through register A with the TPU0A instruction.
The contents of register PU0 is transferred to register A with the TAPU0 instruction.
Table 2.1.1 shows the pull-up control register PU0.

Table 2.1.1 Pull-up control register PU0

Pull-up control register PU0
Ports P1 , P1
2
PU0
3
pull-up transistor control bit
Ports P1 , P1
0
PU0
2
pull-up transistor control bit
Ports P0 , P0
2
PU0
1
pull-up transistor control bit
Ports P0 , P0
0
PU0
0
pull-up transistor control bit
Note: "R" represents read enabled, and "W" represents write enabled.
2-4
is also used as CNTR0, and port D
6
and D functions, set bit 0 (W6
6 7
at reset : 0000
3
1
3
1
4513/4514 Group User's Manual
is also used as CNTR1. Accordingly, when
7
) and bit 2 (W6
0
–P0 and P1
0 3
at RAM back-up : state retained
2
Pull-up transistor OFF
0
Pull-up transistor ON
1
Pull-up transistor OFF
0
Pull-up transistor ON
1
Pull-up transistor OFF
0
Pull-up transistor ON
1
Pull-up transistor OFF
0
Pull-up transistor ON
1
–D
0 7
" or more to register Y.
2
) of timer control register
2
–P1 pull-up transistor.
0 3
, select one
R/W