Clock-Capable Input Pin Placement Rules - Xilinx 7 Series User Manual

Chapter 2: Clock Routing Resources
If it is necessary to drive a CMT from a clock-capable input that is not in the same clock
region, and there is no MMCM/PLL in the same clock region as the clock-capable input,
the attribute CLOCK_DEDICATED_ROUTE = BACKBONE must be set. In this case, the
MMCM or PLL do not properly align outputs to the input clock.
There are limited dedicated resources to drive CMTs in the adjacent clock regions. Some
Xilinx IP uses these resources, thus making them unavailable for additional design uses
and resulting in unroutable designs. If the dedicated routes to the adjacent clock regions
are not available, setting CLOCK_DEDICATED_ROUTE to FALSE allows the local
interconnect logic to be used, although it results in longer, uncompensated delays.

Clock-Capable Input Pin Placement Rules

The two main considerations when manually choosing clock-capable input pins in
advance of creating the initial design are:
•
•
The placement rules shown in
clock-capable input pin selection has access to the desired internal clock network. Each
I/O bank resides in a single clock region.
Note:
placement is chosen properly.
Table 2-1: Clock-Capable Input Placement Rules
Clock Inputs To
I/Os and/or sequential elements
(4)
throughout the device
I/O and/or sequential elements
within a single clock region using
(4)
BUFH
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Ensure that the clock-capable input can connect to the desired clock resource. The
placement rules to ensure connectivity are shown in
Ensure that the desired clock resources are available and not already used by another
portion of the design. The best way to ensure that both external clocks coming in
through clock-capable inputs and internally generated clocks coming from IP do not
run into conflicts accessing the internal clock networks is to build an initial design
containing the desired clock networks and IP, and run it through the implementation
tools. This significantly increases checking and confidence that the pinout will not
need to change due to clocking reasons.
Avoid costly board respins and poor clock timing by ensuring that clock-capable input pinout
Resource Utilization and Placement Rules
Clock-capable input > BUFG > global clock tree
• The clock-capable input must be placed in the same top or
bottom half as the BUFG.
• There are 16 BUFGs in the top half and 16 BUFGs in the
bottom half of each device.
• Each clock region can have up to 12 unique global clocks
and use the horizontal clock lines.
Clock-capable input > BUFH > horizontal clock line
• Clock-capable inputs must be placed in the same clock
region or the horizontally adjacent clock region as the
BUFH.
• There are 12 BUFHs and 12 horizontal clock lines in each
clock region.
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Table 2-1 should be followed to ensure that the
7 Series FPGAs Clocking Resources User Guide
Table 2-1.
Valid
(1) (2) (3)
Clock-Capable
Input Pin
SRCC or MRCC
SRCC or MRCC
UG472 (v1.5) July 13, 2012