Gtx Transceiver Clock Input Smas - Xilinx ML623 User Manual

Table 1-13: GTX Transceiver Pins (Cont'd)

GTX Transceiver Clock Input SMAs

[Figure
The ML623 board provides differential SMA connectors that can be used for connecting an
external function generator to all GTX transceiver reference clock inputs of the FPGA. The
FPGA reference clock pins are connected to the SMA connectors as shown in
Table 1-14: GTX Transceiver Clock Inputs to the FPGA
ML623 Board User Guide
UG724 (v1.1) September 15, 2010
FPGA Pin Net Name
B5 116_RX3_P
B6 116_RX3_N
A3 116_TX3_P
A4 116_TX3_N
1-2, callout 19]
FPGA Pin Net Name
AK6 112_REFCLK0_P
AK5 112_REFCLK0_N
AH6 112_REFCLK1_P
AH5 112_REFCLK1_N
AD6 113_REFCLK0_P
AD5 113_REFCLK0_N
AB6 113_REFCLK1_P
AB5 113_REFCLK1_N
V6 114_REFCLK0_P
V5 114_REFCLK0_N
T6 114_REFCLK1_P
T5 114_REFCLK1_N
P6 115_REFCLK0_P
P5 115_REFCLK0_N
M6 115_REFCLK1_P
M5 115_REFCLK1_N
H6 116_REFCLK0_P
H5 116_REFCLK0_N
F6 116_REFCLK1_P
F5 116_REFCLK1_N
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Detailed Description
SMA Connector Trace Length (Mils)
J143
J142
J140
J139
SMA Connector
J59
J60
J49
J50
J70
J61
J72
J71
J90
J81
J92
J91
J125
J124
J123
J106
J156
J148
J138
J137
9,846
9,837
10,663
10,659
Table 1-14.
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