Fujitsu MB90335 Series Hardware Manual page 109

CHAPTER 3 INTERRUPT
3.8 Interruption by μDMAC
3.8.2.1 DMA Descriptor Channel Specification Register (DCSR)
DMA descriptor channel specification register (DCSR) switches the descriptor of each
channel.
The descriptor is set after the channel is specified by this register.
■ DMA Descriptor Channel Specification Register (DCSR)
bit
00009B
H
R/W: Readable/Writable
[bit15] STP:STP control bit
STP bit
0 [Initial value]
[bit14 to bit12] Reserved: (reserved bits)
These bits are reserved bits.
These bits are always "000
Please write "000
Note:
Do not use any read modify write (RMW) instruction to access the DCSR register.
88
Figure 3.8-2 DMA Descriptor Channel Specification Register
15 14 13
STP
Reserved Reserved Reserved
R/W R/W R/W
STP8 to STP15 is selected as DSSR.
1 STP0 to STP7 is selected as DSSR.
" at the beginning of reading.
B
".
B
FUJITSU MICROELECTRONICS LIMITED
12 11 10
DCSR3 DCSR2 DCSR1 DCSR0
R/W R/W R/W R/W
Function
MB90335 Series
9 8
DCSR
R/W Initial value 00000000
B
CM44-10137-6E