Table of Contents
Advertisement
CHAPTER 3 INTERRUPT
3.3 Interrupt Control Register and Peripheral Function
Table 3.3-3 Correspondence between EI
ICS3
ICS2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
●
2
EI
OS status bits (S1 and S0)
It is a bit only for reading. By examining the value at the end of EI
termination status can be determined. The bit is initialized to "00
relationships between the S0/S1 bits and the EI
Table 3.3-4 Relation between EI
58
2
OS Channel Select Bits and Descriptor Addresses
ICS1
ICS0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S1
S0
0
0
0
1
1
0
1
1
FUJITSU MICROELECTRONICS LIMITED
Channel to be selected
0
0
1
1
0
2
1
3
0
4
1
5
0
6
1
7
0
8
1
9
0
10
1
11
0
12
1
13
0
14
1
15
2
OS status.
2
OS Status Bits and EI
2
When EI
OS in operation or not started.
Stop state by end of counting
Reserved
Stop state by request from peripheral function
MB90335 Series
Descriptor address
000100
000108
000110
000118
000120
000128
000130
000138
000140
000148
000150
000158
000160
000168
000170
000178
2
OS operation, the operating state and/or
" at a reset. Table 3.3-4 shows the
B
2
OS Status
2
OS status
EI
CM44-10137-6E
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Advertisement
Table of Contents
