Fujitsu MB90335 Series Hardware Manual page 207

CHAPTER 10 WATCHDOG TIMER
10.2 Watchdog Timer Control Register (WDTC)
Table 10.2-1 Function of Each Bit of Watchdog Timer Control Register (WDTC)
Bit name
bit7, PONR
bit5 WRST
to ERST
bit3 SRST
bit6 Reserved
bit2 WTE
bit1, WT1
bit0 WT0
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• Read-only bits that indicate reset factors. When a reset factor occurs, the
relevant bit is set to "1".
• The PONR, WRST, ERST and SRST bits are all cleared to "0" after the
Reset factor bits WDTC register is read.
• The contents of the bits other than the PONR bit are not assured at power-on.
Therefore, when the PONR bit is "1", ignore the contents of the bits other
than the PONR bit.
• The reading value is irregular.
Reserved bit
• Writing does not have the influence in the operation.
• Writing "0", activates the watchdog timer (at the first write after reset) or
Watchdog
clears the 2-bit counter (at the second write after reset).
control bit
• There is no influence in the operation in writing "1".
• This is a bit to select the interval time of the watchdog timer.
• The data at the activation of the watchdog timer is valid. Data written after
Interval time
select bits the activation of the watchdog timer is ignored.
• The WT1 and WT0 bit are only for writing.
FUJITSU MICROELECTRONICS LIMITED
MB90335 Series
Functions
CM44-10137-6E