Fujitsu MB90335 Series Hardware Manual page 411

CHAPTER 18 UART
18.2 Block Diagram of UART
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Serial input data register 0, 1 (SIDR0, SIDR1)
The register retains the receive data. The serial input is converted and then stored in this register.
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Serial output data register 0, 1 (SODR0, SODR1)
The register sets the transmit data. Data written to this register is serially converted to be output.
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UART prescaler control register 0, 1 (UTCR0, UTCR1)
Specifies start-up/halt of the communication prescaler, forced reset of UART, selecting of clock sources,
and the rate of division of the machine clock.
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UART prescaler reload register 0, 1 (UTRLR0, UTCR1)
Specifies the division rate of the machine clock.
390 FUJITSU MICROELECTRONICS LIMITED
MB90335 Series
CM44-10137-6E