Table of Contents
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SIDR
Serial Input Data Register 0,1 (SIDR0,SIDR1)
Single Measurement
Single Measurement and Continuous Measurement
.......................................................... 310
Single Shot Mode
Internal Clock Mode (Single Shot Mode)
Single-chip Mode
Connection Example in Single-chip Mode
(when Using User Power)
Pin State in Single-chip Mode
Sleep Mode
Cancellation of Sleep Modes
Transition to Sleep Mode
SLP
Priority Level of STP, SLP, and TMD Bit
SMCS
Serial Mode Control Status Register (SMCS)
SMR
Serial Mode Register 0,1 (SMR0,SMR1)
SODR
Serial Output Data Register 0,1 (SODR0,SODR1)
.......................................................... 401
SOF
..................................................... 279
SOF Interrupt
SOF Interruption FRAME Comparison Register
SOF Interruption FRAME Comparison Register
.......................................... 263
(HFCOMP)
SOF Token
........................................................ 288
SOF Token
Software Interrupt
Operation of Software Interrupt
Precautions on Software Interrupt
Return from Software Interrupt
Start of Software Interrupt
SSB
Bank Registers (PCB, DTB, USB, SSB, ADB)
SSP
User Stack Pointer (USP) and System Stack Pointer (SSP)
............................................................ 32
SSR
Sector Switching Register (SSR0)
Sector Switching Register (SSR0) Setting Procedure
.......................................................... 510
Serial Status Register 0,1 (SSR0,SSR1)
Stack Area
......................................................... 104
Stack Area
Stack Operation
Stack Operation at the Start of Interrupt Processing
.......................................................... 103
Stack Operation when Interrupt Processing Returns
.......................................................... 103
Standby Mode
Cancellation of Standby Mode by Interrupt
Operation Status in Standby Mode
.................................................... 137
Standby Mode
Transition to Standby Mode and Interrupt
610
........... 400
.................. 334
........................ 519
................................ 153
................................. 147
...................................... 146
................. 143
............ 370
.................. 395
................................ 71
............................. 71
................................ 70
....................................... 70
............ 37
........................... 489
.................... 397
............... 154
.......................... 145
................. 154
Start
Start/stop Timing of Shift Operation and Timing of I/O
......................................................... 381
Start Condition
................................................... 447
Start Condition
Startup
......................................... 305
Operation after Startup
State
Read/Reset State in Flash Memory
State Transition
State Transition Diagram
State Transition of Counter Operation
Status Register
Extended Intelligent I/O Service (EI
.................................................. 77
(ISCS)
Stop Condition
................................................... 447
Stop Condition
Stop Mode
Cancellation of Stop Modes
....................................... 149
Transition to Stop Mode
Stop Timing
Start/stop Timing of Shift Operation and Timing of I/O
......................................................... 381
Stops
............................................................... 306
Stops
STP
Priority Level of STP, SLP, and TMD Bit
Structure
Structure of Instruction Map
Suspend
............................................. 235
Suspend Processing
Suspend Operation
.............................................. 283
Suspend Operation
Suspension
....................................... 508
Sector Erase Suspension
Synchronous Mode
Operation in Synchronous Mode (Operation Mode 2)
......................................................... 419
System Configuration
System Configuration and E
......................................................... 468
System Stack Pointer
User Stack Pointer (USP) and System Stack Pointer (SSP)
........................................................... 32
T
TBTC
Time-base Timer Control Register (TBTC)
Time Stamp Register
Time Stamp Register (TMSP)
Time-base Timer
Block Diagram of Time-base Timer
Interrupt of Time-base Timer
Interrupt of Time-base Timer and EI
......................................................... 176
......................... 502
...................................... 151
..................... 330
2
OS) Status Register
.................................. 149
................ 143
.................................. 575
2
PROM Memory Map
............... 174
................................ 208
........................ 172
................................ 176
2
OS, μDMAC
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