Data Programming To Flash Memory - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
22.7.2

Data Programming to Flash Memory

This section explains the procedure for inputting the program command to program
data to flash memory.
■ Data Programming to Flash Memory
• In order to start the data programming automatic algorithm, continuously transmit the program
command in the command sequence table from CPU to flash memory.
• At completion of data programming to a target address in the fourth cycle, the automatic algorithm starts
automatic programming.
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How to specify address
• Only even addresses can be specified for the programming address specified by programming data
cycle. Specifying odd addresses prevents correct writing. Writing to even addresses must be performed
in word data units.
• Programming is possible in any address order or even beyond sector boundaries. However, execution of
one programming command permits programming of data for only one word.
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Notes on data programming
• The bit data "0" cannot be returned to the bit data "1" by programming. When the bit data "0" is
programmed to data "1", the data polling flag (DQ7) or toggling (DQ6) is not terminated and the flash
memory is considered faulty; the timing limit over flag (DQ5) is determined as an error.
• When data is read in the read/reset state, the bit data remains "0". To return the bit data to "1" from "0",
erase flash memory data.
• All commands are ignored during automatic programming.
• If a hardware reset occurs during programming, data being programmed to addresses is not assured.
Please re-try from chip delete or sector erase.
■ Data Programming Procedure
• Figure 22.7-1 gives an example of the procedure for programming data into flash memory. The
hardware sequence flags can be used to check the operating state of the automatic algorithm in flash
memory. The data polling flag (DQ7) is used for checking the completion of programming to flash
memory in this example.
• Flag check data should be read from the address where data was last written.
• Because the data polling flag (DQ7) and the timing limit over flag (DQ5) change at the same time, the
data polling flag (DQ7) must be checked even when the timing limit over flag (DQ5) is "1".
• Similarly, since the toggle bit flag (DQ6) stops toggling at the same time the timing limit over flag
(DQ5) changes to "1", the toggle bit flag (DQ6) must be checked.
CM44-10137-6E FUJITSU MICROELECTRONICS LIMITED
CHAPTER 22 DUAL OPERATION FLASH MEMORY
22.7 Details of Programming/Erasing Flash Memory
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