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APPENDIX B Instructions
2
B.8 F
MC-16LX Instruction List
Table B.8-13 31 Branch 1 Instructions
Mnemonic
#
BZ/BEQ
rel
2
BNZ/
rel
2
BNE
BC/BLO rel
2
BNC/
rel
2
BHS
BN
rel
2
BP
rel
2
BV
rel
2
BNV
rel
2
BT
rel
2
BNT
rel
2
BLT
rel
2
BGE
rel
2
BLE
rel
2
BGT
rel
2
BLS
rel
2
BHI
rel
2
BRA
rel
2
JMP
@A
1
JMP
addr16
3
JMP
@ear
2
JMP
@eam
2+
JMPP
@ear *3
2
JMPP
@eam *3
2+
JMPP
addr24
4
CALL
@ear *4
2
CALL
@eam *4
2+
CALL
addr16 *5
3
CALLV
#vct4 *5
1
CALLP
@ear *6
2
CALLP
@eam *6
2+
CALLP
addr24 *7
4
*1: 4 when a branch is made; otherwise, 3
*2: 3 × (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
570
~
RG
B
*1
0
0
Branch on (Z) = 1
*1
0
0
Branch on (Z) = 0
*1
0
0
Branch on (C) = 1
*1
0
0
Branch on (C) = 0
*1
0
0
Branch on (N) = 1
*1
0
0
Branch on (N) = 0
*1
0
0
Branch on (V) = 1
*1
0
0
Branch on (V) = 0
*1
0
0
Branch on (T) = 1
*1
0
0
Branch on (T) = 0
*1
0
0
Branch on (V) xor (N) = 1
*1
0
0
Branch on (V) xor (N) = 0
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
*1
0
0
Branch on (C) or (Z) = 1
*1
0
0
Branch on (C) or (Z) = 0
*1
0
0
Unconditional branch
word (PC) ← (A)
2
0
0
word (PC) ← addr16
3
0
0
word (PC) ← (ear)
3
1
0
word (PC) ← (eam)
4+(a)
0
(c)
word (PC) ← (ear), (PCB) ← (ear+2)
5
2
0
word (PC) ← (eam), (PCB) ← (eam+2)
6+(a)
0
(d)
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
4
0
0
word (PC) ← (ear)
6
1
(c)
2 × (c)
word (PC) ← (eam)
7+(a)
0
word (PC) ← addr16
6
0
(c)
2 × (c)
7
0
Vector call instruction
2 × (c)
word (PC) ← (ear), (PCB) ← (ear+2)
10
2
word (PC) ← (eam), (PCB) ← (eam+2)
11+(a)
0
*2
2 × (c)
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
10
0
FUJITSU MICROELECTRONICS LIMITED
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