Fujitsu MB90335 Series Hardware Manual page 260

MB90335 Series
■ Data Number Automatic Transfer Mode
It sets the total number of pieces of data to be transferred in DMA and sets the transfer enable bit in
advance. When DMAE is enabled and the DRQ is set after transfer from the HOST has been completed,
the interrupt cause is automatically cleared when data whose number of pieces is equal to the PKS in the
EP1 to EP5 control registers (EPxC) has been transferred (Whether the DRQ flag is actually cleared
depends on the fact that both buffers in a double buffer are empty or full). Subsequently, when transfer
from the HOST has been completed, repeat the similar process until data equivalent to the number of pieces
of transfer data predefined in DMA. has been transferred. Meanwhile, any intervention from CPU is not
required, and transfer will be completed with only one setting, which is the automatic transfer mode. If the
device performs the next transfer, it sets μDMAC again and enables DMA when a CPU interrupt is raised
when the last data has been transferred, and returns from the CPU interrupt. Since the data number
automatic transfer mode is used for DMAE=1, only buffer access to endpoint 1 to endpoint5 is enabled.
Timing by which the buffer is accessed in OUT direction and IN direction is shown as follows.
Figure 11.4-17 OUT Direction (Host PC → Device) Forwarding
Host PC
Device
Device
Host PC
DMAE
DRQIE
DRQ
SIZE
DER(Enx)
In both OUT- direction and IN- direction transfer, a USB device must perform processes in the following
steps:
1. It sets the total number of pieces of data to be transferred in the data counter register DDCT in DMA
and enables DMA with the DER register.
2. DMAE and DRQIE, are permitting set.
3. Once transfer has been completed, it sets μDMAC again with an interrupt due to the corresponding
interrupt factor in the DSR register of μDMAC and clear the flag if necessary, and returns from the
interrupt process.
*: It consists the double buffers of EP1 to EP5. It should be cleared only (auto-reset) when one buffer that
is not being accessed is empty and data is read from another buffer being accessed (Automatic clear)
and cannot be cleared if one buffer that is not being accessed has data left to be read. It continuously
enters the DRQ interrupt process.
CM44-10137-6E
OUT packet
OUT DATA0
DRQ flag *
ACK
Automatic
clear
Read PKS part of
DMA receive buffer
FUJITSU MICROELECTRONICS LIMITED
11.4 Operation Explanation of USB Function
Last OUT packet
OUT DATA1
DATA0
CHAPTER 11 USB FUNCTION
DRQ flag *
Automatic
ACK
clear
DATA1
Read the rest of
DMA receive buffer
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