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2
CHAPTER 19 I
C INTERFACE
2
19.2 I
C Interface Register
•
Condition 2 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur
When an instruction which generates a start condition by enabling I
(setting the MSS bit in the IBCR0 register to "1") with the I
This is because, as shown in Figure 19.2-5, when the other master on the I
2
with I
C disabled (EN bit=0), the I
bit =0).
Figure 19.2-5 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur
SCL0 pin
SDA0 pin
EN bit
MSS bit
AL bit
BB bit
INT bit
If a symptom as described above can occur, follow the procedure below for software processing.
1. Execute the instruction that generates a start condition (set the MSS bit to "1").
2. Use, for example, the timer function to wait for the time* for three-bit data transmission at the I
frequency set in the ICCR0 register.
Example: Time for three-bit data transmission at an I
3
)}x3=30 μs
{1/(100x10
3. Check the AL and BB bits in the IBSR0 register and, if the AL and BB bits are "1" and "0", respectively, set
the EN bit in the ICCR0 register to "0" to initialize I
processing.
440
2
C bus enters the occupied state with no start condition detected (BB
The INT bit interrupt does not occur
Start Condition
in the ninth clock cycle.
SLAVE ADDRESS
FUJITSU MICROELECTRONICS LIMITED
2
C operation (EN bit=1) is executed
2
C bus occupied by another master.
ACK
DATA
2
C transfer frequency of 100 kHz
2
C. When the AL and BB bits are not so, perform normal
MB90335 Series
2
C bus starts communication
Stop Condition
ACK
0
0
2
C transfer
CM44-10137-6E
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