Fujitsu MB90335 Series Hardware Manual page 111

CHAPTER 3 INTERRUPT
3.8 Interruption by μDMAC
3.8.2.2 DMA Status Register (DSRH/DSRL)
DMA status register (DSRH/DSRL) indicates that the DMA transfer ended. When "1" is
set to this register, the interrupt is generated at the same time.
■ Bit Configuration of DMA Status Register (DSRH/DSRL)
Figure 3.8-3 Bit Configuration of DMA Status Register (DSRH/DSRL)
bit 15
00009D
H DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9
R/W
7
bit
00009C
H
DTE7
R/W
R/W: Readable/Writable
[bit15 to bit0] DTEx: DMA Status
DTEx bit
The DMA transfer has not ended.
0 [Initial value]
Please write "0" when DTEx is "0".
Indicates that DMA transfer was completed and an interrupt request is being executing.
1 The DMA transfer due to the STOP request except last transfer does not set 1 to this bit.
When DTEx is "1", writing "0" clears it to "0" and writing "1" holds the previous data.
Note:
To write data to the DSRH/DSRL, use a read-modify-write (RMW) instruction.
90
14 13 12
R/W R/W R/W
6 5 4
DTE6 DTE5 DTE4
R/W R/W R/W
FUJITSU MICROELECTRONICS LIMITED
11 10 9
R/W R/W R/W
3 2 1
DTE3 DTE2 DTE1
R/W R/W R/W
Function
MB90335 Series
8
DTE8
DSRH
R/W Initial value 00000000
0
DSRL
DTE0
R/W Initial value 00000000
CM44-10137-6E
B
B