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CHAPTER 15 8/16-BIT PPG TIMER
15.2 Registers of 8/16-bit PPG Timer
[bit4 to bit2] PCM2 to PCM0:ppg Count Mode (count clock selection)
These bits select the down counter operation clock of ch.0 and ch.2.
PCM2
0
0
0
0
1
1
• These bits are initialized to "000
• Reading and writing are allowed.
[bit1, bit0] Reserved bits
It is Reserved bit. Always set these bits to "00
350
PCM1
PCM0
0
0
Peripheral Clock (41.6 ns machine clock 24 MHz time)
0
1
Peripheral Clock /2 (83.3 ns machine clock 24 MHz time)
1
0
Peripheral Clock /4 (167 ns machine clock 24 MHz time)
1
1
Peripheral Clock /8 (333 ns machine clock 24 MHz time)
0
0
Peripheral Clock /16 (667 ns machine clock 24 MHz time)
Input clock from time-base counter
1
1
9
× 167 ns=85 μs original oscillation 6 MHz time)
(2
" at reset.
B
FUJITSU MICROELECTRONICS LIMITED
Operating mode
".
B
MB90335 Series
CM44-10137-6E
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