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MB90335 Series
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Transmission Operation
• Sending data is written in the serial output data registers 0, 1 (SODR0, SODR1) in the state of "1" being
set to the sending data empty flag bit (SSR0, SSR1: TDRE).
• When the sending data is written, and the bit of the serial control register indicating that sending
operation is enabled (SCR0, SCR1: TXE) is set to "1", then sending starts.
• When the sending data is written to the serial output data register, the sending data empty flag bit (SSR0,
SSR1: TDRE) is once cleared to "0".
• When the sending data is transferred from the serial output data registers 0, 1 (SODR0, SODR1) to the
sending shift register, the sending data empty flag bit (SSR0, SSR1: TDRE) is set to "1" again.
• When the sending data is transferred from the serial output data registers 0, 1 (SODR0, SODR1) to the
sending shift register, the sending data empty flag bit (SSR0, SSR1: TDRE) is set to "1" again.
• When the bit indicating that the sending interrupts (SSR0, SSR1: TIE) is enabled has already been set to
"1", a sending interrupt request is generated if the sending data empty flag bit (SSR0, SSR1: TDRE) is
set to "1".In interrupt processing, the following data can be written to the serial output data registers 0, 1
(SODR0, SODR1).
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Reception Operation
• Receiving operation are always performed when the receiving operations are set to be enabled (SCR0,
SCR1: RXE=1).
• When the start bit of the receiving data is detected, one frame of data is received in the serial input data
registers 0, 1 (SIDR0, SIDR1) based on the data format that is set in the serial input control register 0, 1
(SCR0, SCR1).
• One frame of data reception is completed, the receiving data full flag bit (SSR0, SSR1: RDRF) is set to "1".
• When reading receiving data, check the state of error flags of the serial status registers 0, 1 (SSR0, SSR1).
If receiving is successful, then read the receiving data from the serial input data register. When a
reception error occurs, perform error handling.
• When the receiving data has been read, the receiving data full flag bit (SSR0, SSR1: RDRF) is cleared to
"0".
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Stop Bit
One bit or two bits length can be selected. However, the receive side always detects only the first bit.
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Error detection
In mode 0, parity, overrun, and framing error can be detected.
In the operation mode 1, overrun and framing errors can be detected. But parity errors cannot be detected.
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Parity bit
The addition of a parity bit can be set only in operation mode 0. The parity addition enable bit (SCR0,
SCR1: PEN) and parity select bit (SCR0, SCR1:P) can be used to select whether to use parity and to set the
even or odd parity, respectively.
In the operation mode 1 and 2, parity cannot be appended.
Figure 18.7-2 shows the sending and receiving data when parity bits are valid.
CM44-10137-6E
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 18 UART
18.7 Explanation of Operation of UART
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