Fujitsu MB90335 Series Hardware Manual page 76

MB90335 Series
Figure 3.3-2 Interrupt Control Register (ICR00 to ICR15) at Read
At read
Address
MSB
0000B0
H
to
0000BF
H
MSB : The most significant bit
LSB
: The least significant bit
: Undefined
: Initial value
CM44-10137-6E
S1 S0 ISE IL2 IL1
IL2
0
0
0
0
1
1
1
1
ISE
0
1
S1
0
0
1
1
FUJITSU MICROELECTRONICS LIMITED
3.3 Interrupt Control Register and Peripheral Function
Initial value
LSB
IL0
- - 000111
B
IL1 IL0
Interrupt level set bit
0 0
Interrupt level 0 (Highest)
0 1
1 0
1 1
0 0
0 1
1 0
Interrupt level 7 (No interrupt)
1 1
2
EI OS enable bit
Activate interrupt sequence during generation of an interrupt.
2
Activate EI OS during generation of an interrupt.
2
S0
EI OS status
2
0
EI OS operation in progress or EI
1 Stop status by count end
0
Reserved
1
Stop status by request from peripheral function
CHAPTER 3 INTERRUPT
2
OS not activated
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