Fujitsu MB90335 Series Hardware Manual page 201

CHAPTER 9 TIME-BASE TIMER
9.6 Precautions when Using Time-base Timer
■ Operations of Time-base Timer
Operations in the following situations are shown in Figure 9.6-1.
• At a power-on reset occurs.
• At a transition to sleep mode during the operation of interval timer function
• At a transition to stop mode.
• At a counter clear request occurs.
The transition to the stop mode clears the time-base timer, terminating operations. Upon the recovery from
the stop mode, oscillation stabilization wait time is counted with the time-base timer.
Counter value
3FFFF
Oscillation
stabilization
wait overflow
00000
Power-on reset
TBOF bit
TBIE bit
SLP bit
(LPMCR register)
STP bit
(LPMCR register)
When setting "11 " to interval time selection bits (TBTC: TBC1, TBC0) of time-base
B
timer control register (2
: Oscillation stabilization wait time
: Oscillation clock
HCLK
180
Figure 9.6-1 Operations of Time-base Timer
H
H
CPU operation
start
(
TBTC : TBC1, TBC0=11
(Option)
Clear by interrupt routine
Interval interrupt sleep cancellation
19
/HCLK)
FUJITSU MICROELECTRONICS LIMITED
Clear by transition
to the stop mode
Interval cycle
)
B
Sleep
Stop cancellation by External interrupt
MB90335 Series
Counter clear
(
TBTC : TBR=0
Stop
CM44-10137-6E
)