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CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5 Standby Mode
Notes:
•
When handling an interrupt, the CPU usually services the interrupt after executing the instruction
that follows the one specifying the stop mode.
•
In PLL stop mode, the main clock and PLL multiplier circuit remain stopped. When the CPU
returns from PLL stop mode, therefore, it is necessary to allow for the main clock oscillation
stabilization wait time and PLL clock oscillation stabilization wait time. In this case, the oscillation
stabilization wait time concurrently counts the main clock oscillation stabilization wait time and the
PLL clock oscillation stabilization wait time, according to the value specified in the oscillation
stabilization wait time selection bit (CKSCR: WS1, WS0) of the clock selection register, thus the
CKSCR: WS1, WS0 bit must be set in accordance with the longer oscillation stabilization wait
time. However, as the PLL clock stabilization wait time requires at least 2
the CKSCR: WS1, WS0 bit to "10
Figure 6.5-2 shows the cancellation operation of the stop mode.
RST Pin
Stop mode
Main clock
PLL clock
CPU clock
CPU operation
150
B
Figure 6.5-2 Cancellation of Stop Mode (External Reset)
Stop mode cancellation
FUJITSU MICROELECTRONICS LIMITED
" or "11
".
B
Oscillation stabilizing wait
suspension
Reset cancellation
MB90335 Series
14
/HCLK, be sure to set
oscillation
Main clock
Processing
Reset sequence
CM44-10137-6E
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