Uart Interrupt - Fujitsu MB90335 Series Hardware Manual

CHAPTER 18 UART

18.5 UART Interrupt

18.5 UART Interrupt
The UART support reception and transmission interrupts, capable of generating an
interrupt request in the following conditions:
• Where the receiving data is set to the serial input data registers 0, 1 (SIDR0, SIDR1),
or an receiving error has occurred.
• When data to transmit is transferred from serial output data register 0, 1 (SODR0,
SODR1) to the transmission shift register.
Also, support for each extended intelligent I/O service (EI
■ UART Interrupt
Table 18.5-1 shows the interrupt control bit and interrupt factor of UART.
Table 18.5-1 Interrupt Control Bit of UART and Interruption Factor
Transmission
/
Interrupt
Reception
flag bit
RDRF
ORE
Reception
FRE
PE
Transmission TDRE
❍
: Using bit
: Unused bit
●
Reception Interrupt
When receiving interrupts are enabled (SSR0, SSR1: RIE=1) and if either completion of data reception
(SSR0, SSR1: RDRF=1), an overrun error (SSR0, SSR1: ORE=1), a framing error (SSR0, SSR1: FRE=1),
or a parity error (SSR0, SSR1: PE=1) occurs, then an receiving interrupt request is generated.
When the receiving data full flag (SSR0, SSR1: RDRF) reads the serial input data registers 0, 1 (SIDR0,
SIDR1), it is automatically cleared to "0". Each reception error flag (SSR0, SSR1: PE, ORE, FRE) is
cleared to "0" when "0" is written to the reception error flag clear bit (SCR0, SCR1: REC).
In the case that any receiving error (a parity error, an overrun error, a framing error) occurs, handle such
error where necessary, and then write "0" in the receiving error flag clear bit (SCR0, SCR1: REC) to clear
each of the receiving error flags.
404
Serial Status Register 0, 1 (SSR0, SSR1)
Operating mode
Interrupt cause
0 1 2
Load Receive Data to
❍ ❍ ❍
the buffer (SIDR0,
SIDR1)
Generating Overrun
❍ ❍ ❍
error
Generating Framing
❍ ❍
error
❍
Generating parity error
Transmission buffer
❍ ❍ ❍
(SODR0, SODR1) is
empty.
FUJITSU MICROELECTRONICS LIMITED
MB90335 Series
2
OS), μDMAC.
Interruption
permission Clear Interrupt flag
bit
• Reading receive data
• Reset
• Writing "0" to the
RIE
reception error flag
clear bit (SCR0, SCR1:
REC)
• Reset
• Writing transmit data
TIE
• Reset
CM44-10137-6E