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CHAPTER 12 USB HOST
12.5 Operation of USB HOST
12.5.3
Token Packet
If you execute any of an IN token, OUT token, and SETUP token in the host mode, a
token packet is started when you set necessary data in the host token register
(HTOKEN) after you set the PKS bit of the EP1 control register (EP1C) or EP2 control
register (EP2C) based on the host address register (HADR) and the DIR bit in EP1C. In
handling an SOF token, you must set necessary data in the host token register
(HTOKEN) after configuring the FRAME setting register (HFRAME) and EOF setting
register (HEOF). If registers (HADR, EP1C, EP2C, HFRAME, and HEOF) have not been
changed, setting them is not required.
■ Setting of Token Packet
For the IN token, OUT token, and SETUP token, set the destination address to the host address register
(HADR), and set the maximum bytes of one packet to the PKS bit of the EP1 control register (EP1C) or the
EP2 control register based on the token to be executed and the DIR bit of the EP1 control register.
If the DIR bit of the EP1 control register (EP1C) is "1", the buffer for endpoint 1 is used as an OUT-
direction buffer and the one for endpoint 2 is used as an IN- direction buffer. Then, set the DIR bit of the
EP2 control register (EP2C) to "0".
If the DIR bit of the EP1 control register (EP1C) is "0", the buffer for endpoint 1 is used as an IN- direction
buffer and the one for endpoint 2 is used as an OUT- direction buffer. Then, set the DIR bit of the EP2
control register (EP2C) to "1".
If you want to use the buffer for endpoint 1, you must ensure that the DRQ bit of EP1 status register (EP1S)
is set to "0" and if you want to use the buffer for endpoint 2, you must ensure that the DRQ bit of EP2
status register (EP2S) is set to "1," before setting the target endpoint, token, and toggle data in the host
token endpoint register (HTOKEN). The USB circuit sends out a token packet in the order of a Sync, token,
address, endpoint, CRC5, and EOP based on the specified token (a Sync, CRC5, and EOP are automatically
sent). After one packet is ended, the CMPIRQ bit of the host interrupt register (HIRQ) becomes "1", and
the TKNEN bit of the host token endpoint register (HTOKEN) is set to 000
Interrupt"). At that time, if the CMPIRE bit of the host control register 0 (HCNT0) is "1", an interrupt
occurs. To clear the interrupt, write "0" to the CMPIRQ bit of the host interrupt register (HIRQ).
Figure 12.5-3 Example of Register Setting until Execution of IN/OUT/SETUP Token
(when a change is required)
Register write signal
In the case of an SOF token, when you set an EOF time and FRAME number in the EOF setting register
(HEOF) and FRAME setting register (HFRAME), and write the code of the SOF token to the TKNEN bits
of the host token endpoint register (HTOKEN), a Sync, SOF token, FRAME number, CRC5, and EOP will
be sent out and the SOFBUSY bit of the host state status register (HSTATE) is set to "1" and HFRAME is
274
Write to HADR
Write to EP1C or EP2C
(when a change is required)
Confirm the status of the buffer for endpoint 1/endpoint 2
FUJITSU MICROELECTRONICS LIMITED
MB90335 Series
(See Section "12.5.7 SOF
B
Write to HTOKEN
CM44-10137-6E
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