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CHAPTER 11 USB FUNCTION
11.3 Registers of USB Function
[bit15] BFINI: Transmission/receive buffer initialization bit
The transmission and reception buffer of the forwarding data is initialized. The BFINI bit is
automatically set by setting the RST bit in the UDC control register (UDCC). Consequently, when the
reset operation has been performed with the RST bit, clear the RST bit before clearing the BFINI bit.
BFINI
0
1
Note:
The transmission/receive buffer for EP1 to EP5 has a configuration of double buffers and
initialization by the BFINI bit initializes the double buffers at once and also initializes the DRQ and
SPK bits. You must initialize the buffers when you have set the STAL bit after you ensure that the
DRQ bit is set and the BUSY bit shows no access from the HOST.
[bit14] DRQIE: Packet forwarding interruption permission bit
It allows an interrupt due to the interrupt factor for the EP1 to EP5 status register "DRQ" to be
generated.
DRQIE
0
1
Note:
If you use the automatic buffer transfer mode (DMAE=1), you must enable the settings of DMA and
transfer before enabling the DRQIE bit.
[bit13] SPKIE: Short packet interruption permission bit
It allows an interrupt due to the interrupt factor for the EP1 to EP5 status register "SPK" to be
generated.
SPKIE
0
1
[bit12] Reserved bit
This bit is reserved bit. Writing has no effect on the operation. Reading is undefined.
220
Initialization of transmitting and receiving buffer
Interrupt disabled by DRQ factor
Interruption permission by DRQ factor
Interrupt disabled by SPK factor
Interruption permission by SPK factor
FUJITSU MICROELECTRONICS LIMITED
Operating mode
Cancelling Initialization
Operating mode
Operating mode
MB90335 Series
CM44-10137-6E
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